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RT8862 1 ds8862-01 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. advanced 4/3/2/1-phase pwm controller with embedded drivers for cpu core power supply general description the RT8862 is an advanced 4/3/2/1-phase synchronous buck controller with 2 integrated mosfet drivers for intel vr11/vr10 and amd k8/k8_m2 cpus power application. RT8862 adopts state-of-the-art dynamic phase control capability. that achieves high efficiency over wide load range. it uses differential inductor dcr current sense to achieve phase current balance and active voltage positioning. other features include adjustable operating frequency, adjustable soft start, power good indication, external error-amp compensation, over voltage protection, over current protection and enable/shutdown for various application. RT8862 comes to a small footprint with wqfn-48l 7x7 package. applications z desktop cpu core power z low voltage, high current dc/ dc converter pin configurations wqfn-48l 7x7 (top view) imon isp4 isn4 isn3 isp3 isp2 vcc5 isn2 isn1 isp1 vrhot tsen ps vidsel vid0 vid1 vid2 en/vtt vid3 vid4 vid5 vid6 vid7 pwrgd phase1 ugate1 pwm4 pwm3 boot2 ugate2 phase2 lgate2 lgate1 vcc12 boot1 fbrtn ss/en qr2 imonfb imaxpsi imax adj rt ofs comp fb qr1 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 gnd 49 psi features z z z z z support dynamic phase control z z z z z 12v power supply voltage z z z z z 4/3/2/1-phase power conversion z z z z z 2 embedded mosfet drivers z z z z z internal regulated 5v output z z z z z vid table for intel vr11.1/vr10.x and amd k8/ k8_m2 cpus z z z z z continuous differential inductor dcr current sense z z z z z adjustable soft start z z z z z adjustable frequency (300khz typ.) z z z z z power good indication z z z z z adjustable over current protection z z z z z over voltage protection z z z z z vrhot sensing with external thermistor z z z z z imon output current indication z z z z z power state indicator (psi) z z z z z small 48-lead wqfn package z z z z z rohs compliant and halogen free package type qw : wqfn-48l 7x7 (w-type) RT8862 lead plating system g : green (halogen free and pb free)
RT8862 2 ds8862-01 april 2011 www.richtek.com typical application circuit a d j v c c 5 u g a t e 1 u g a t e 2 i s n 1 r t 8 8 6 2 o f s i m a x b o o t 2 l g a t e 1 i s p 2 s s / e n p h a s e 2 i s n 2 c o m p f b r t n b o o t 1 p h a s e 1 l g a t e 2 i s p 1 l 1 l 2 n t c 1 load f b v i d [ 7 : 0 ] e n / v t t p s i p w r g d i m a x p s i i m o n f b i m o n p s n t c 2 t s e n 5 v v r h o t e n / v t t 36 35 34 33 32 30 29 28 27 37 47 48 1 4 5 6 7 9 10 11 12 24 23 22 21 20 19 18 13 38 to 45 v i n v i n v c c 1 2 g n d 1 2 v e x p o s e d p a d ( 4 9 ) 31 i s n 4 i s p 4 15 14 p w m 3 i s n 3 i s p 3 p w m 4 l 3 1 2 v l 4 1 2 v rt9619 vcc pwm boot ugate phase lgate 1 2 v gnd vcc pwm boot ugate phase lgate 1 2 v gnd rt9619 q r 1 26 25 2 17 16 r t 8 5 v v c c 5 / v t t 5 v v i d s e l 46 q r 2 3 v r h o t v o u t v c c _ s n s v s s _ s n s
RT8862 3 ds8862-01 april 2011 www.richtek.com table 1. vr11.1 vid code table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 0 0 0 0 0 0 0 off 0 0 0 0 0 0 0 1 off 0 0 0 0 0 0 1 0 1.60000 0 0 0 0 0 0 1 1 1.59375 0 0 0 0 0 1 0 0 1.58750 0 0 0 0 0 1 0 1 1.58125 0 0 0 0 0 1 1 0 1.57500 0 0 0 0 0 1 1 1 1.56875 0 0 0 0 1 0 0 0 1.56250 0 0 0 0 1 0 0 1 1.55625 0 0 0 0 1 0 1 0 1.55000 0 0 0 0 1 0 1 1 1.54375 0 0 0 0 1 1 0 0 1.53750 0 0 0 0 1 1 0 1 1.53125 0 0 0 0 1 1 1 0 1.52500 0 0 0 0 1 1 1 1 1.51875 0 0 0 1 0 0 0 0 1.51250 0 0 0 1 0 0 0 1 1.50625 0 0 0 1 0 0 1 0 1.50000 0 0 0 1 0 0 1 1 1.49375 0 0 0 1 0 1 0 0 1.48750 0 0 0 1 0 1 0 1 1.48125 0 0 0 1 0 1 1 0 1.47500 0 0 0 1 0 1 1 1 1.46875 0 0 0 1 1 0 0 0 1.46250 0 0 0 1 1 0 0 1 1.45625 0 0 0 1 1 0 1 0 1.45000 0 0 0 1 1 0 1 1 1.44375 0 0 0 1 1 1 0 0 1.43750 0 0 0 1 1 1 0 1 1.43125 0 0 0 1 1 1 1 0 1.42500 0 0 0 1 1 1 1 1 1.41875 0 0 1 0 0 0 0 0 1.41250 0 0 1 0 0 0 0 1 1.40625 0 0 1 0 0 0 1 0 1.40000 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 0 1 0 0 0 1 1 1.39375 0 0 1 0 0 1 0 0 1.38750 0 0 1 0 0 1 0 1 1.38125 0 0 1 0 0 1 1 0 1.37500 0 0 1 0 0 1 1 1 1.36875 0 0 1 0 1 0 0 0 1.36250 0 0 1 0 1 0 0 1 1.35625 0 0 1 0 1 0 1 0 1.35000 0 0 1 0 1 0 1 1 1.34375 0 0 1 0 1 1 0 0 1.33750 0 0 1 0 1 1 0 1 1.33125 0 0 1 0 1 1 1 0 1.32500 0 0 1 0 1 1 1 1 1.31875 0 0 1 1 0 0 0 0 1.31250 0 0 1 1 0 0 0 1 1.30625 0 0 1 1 0 0 1 0 1.30000 0 0 1 1 0 0 1 1 1.29375 0 0 1 1 0 1 0 0 1.28750 0 0 1 1 0 1 0 1 1.28125 0 0 1 1 0 1 1 0 1.27500 0 0 1 1 0 1 1 1 1.26875 0 0 1 1 1 0 0 0 1.26250 0 0 1 1 1 0 0 1 1.25625 0 0 1 1 1 0 1 0 1.25000 0 0 1 1 1 0 1 1 1.24375 0 0 1 1 1 1 0 0 1.23750 0 0 1 1 1 1 0 1 1.23125 0 0 1 1 1 1 1 0 1.22500 0 0 1 1 1 1 1 1 1.21875 0 1 0 0 0 0 0 0 1.21250 0 1 0 0 0 0 0 1 1.20625 0 1 0 0 0 0 1 0 1.20000 0 1 0 0 0 0 1 1 1.19375 0 1 0 0 0 1 0 0 1.18750 0 1 0 0 0 1 0 1 1.18125 to be continued
RT8862 4 ds8862-01 april 2011 www.richtek.com vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 1 0 0 0 1 1 0 1.17500 0 1 0 0 0 1 1 1 1.16875 0 1 0 0 1 0 0 0 1.16250 0 1 0 0 1 0 0 1 1.15625 0 1 0 0 1 0 1 0 1.15000 0 1 0 0 1 0 1 1 1.14375 0 1 0 0 1 1 0 0 1.13750 0 1 0 0 1 1 0 1 1.13125 0 1 0 0 1 1 1 0 1.12500 0 1 0 0 1 1 1 1 1.11875 0 1 0 1 0 0 0 0 1.11250 0 1 0 1 0 0 0 1 1.10625 0 1 0 1 0 0 1 0 1.10000 0 1 0 1 0 0 1 1 1.09375 0 1 0 1 0 1 0 0 1.08750 0 1 0 1 0 1 0 1 1.08125 0 1 0 1 0 1 1 0 1.07500 0 1 0 1 0 1 1 1 1.06875 0 1 0 1 1 0 0 0 1.06250 0 1 0 1 1 0 0 1 1.05625 0 1 0 1 1 0 1 0 1.05000 0 1 0 1 1 0 1 1 1.04375 0 1 0 1 1 1 0 0 1.03750 0 1 0 1 1 1 0 1 1.03125 0 1 0 1 1 1 1 0 1.02500 0 1 0 1 1 1 1 1 1.01875 0 1 1 0 0 0 0 0 1.01250 0 1 1 0 0 0 0 1 1.00625 0 1 1 0 0 0 1 0 1.00000 0 1 1 0 0 0 1 1 0.99375 0 1 1 0 0 1 0 0 0.98750 0 1 1 0 0 1 0 1 0.98125 0 1 1 0 0 1 1 0 0.97500 0 1 1 0 0 1 1 1 0.96875 0 1 1 0 1 0 0 0 0.96250 0 1 1 0 1 0 0 1 0.95625 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 0 1 1 0 1 0 1 0 0.95000 0 1 1 0 1 0 1 1 0.94375 0 1 1 0 1 1 0 0 0.93750 0 1 1 0 1 1 0 1 0.93125 0 1 1 0 1 1 1 0 0.92500 0 1 1 0 1 1 1 1 0.91875 0 1 1 1 0 0 0 0 0.91250 0 1 1 1 0 0 0 1 0.90625 0 1 1 1 0 0 1 0 0.90000 0 1 1 1 0 0 1 1 0.89375 0 1 1 1 0 1 0 0 0.88750 0 1 1 1 0 1 0 1 0.88125 0 1 1 1 0 1 1 0 0.87500 0 1 1 1 0 1 1 1 0.86875 0 1 1 1 1 0 0 0 0.86250 0 1 1 1 1 0 0 1 0.85625 0 1 1 1 1 0 1 0 0.85000 0 1 1 1 1 0 1 1 0.84375 0 1 1 1 1 1 0 0 0.83750 0 1 1 1 1 1 0 1 0.83125 0 1 1 1 1 1 1 0 0.82500 0 1 1 1 1 1 1 1 0.81875 1 0 0 0 0 0 0 0 0.81250 1 0 0 0 0 0 0 1 0.80625 1 0 0 0 0 0 1 0 0.80000 1 0 0 0 0 0 1 1 0.79375 1 0 0 0 0 1 0 0 0.78750 1 0 0 0 0 1 0 1 0.78125 1 0 0 0 0 1 1 0 0.77500 1 0 0 0 0 1 1 1 0.76875 1 0 0 0 1 0 0 0 0.76250 1 0 0 0 1 0 0 1 0.75625 1 0 0 0 1 0 1 0 0.75000 1 0 0 0 1 0 1 1 0.74375 1 0 0 0 1 1 0 0 0.73750 1 0 0 0 1 1 0 1 0.73125 to be continued
RT8862 5 ds8862-01 april 2011 www.richtek.com vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 1 0 0 0 1 1 1 0 0.72500 1 0 0 0 1 1 1 1 0.71875 1 0 0 1 0 0 0 0 0.71250 1 0 0 1 0 0 0 1 0.70625 1 0 0 1 0 0 1 0 0.70000 1 0 0 1 0 0 1 1 0.69375 1 0 0 1 0 1 0 0 0.68750 1 0 0 1 0 1 0 1 0.68125 1 0 0 1 0 1 1 0 0.67500 1 0 0 1 0 1 1 1 0.66875 1 0 0 1 1 0 0 0 0.66250 1 0 0 1 1 0 0 1 0.65625 1 0 0 1 1 0 1 0 0.65000 1 0 0 1 1 0 1 1 0.64375 1 0 0 1 1 1 0 0 0.63750 1 0 0 1 1 1 0 1 0.63125 1 0 0 1 1 1 1 0 0.62500 1 0 0 1 1 1 1 1 0.61875 1 0 1 0 0 0 0 0 0.61250 1 0 1 0 0 0 0 1 0.60625 1 0 1 0 0 0 1 0 0.60000 1 0 1 0 0 0 1 1 0.59375 1 0 1 0 0 1 0 0 0.58750 1 0 1 0 0 1 0 1 0.58125 1 0 1 0 0 1 1 0 0.57500 1 0 1 0 0 1 1 1 0.56875 1 0 1 0 1 0 0 0 0.56250 1 0 1 0 1 0 0 1 0.55625 1 0 1 0 1 0 1 0 0.55000 1 0 1 0 1 0 1 1 0.54375 1 0 1 0 1 1 0 0 0.53750 1 0 1 0 1 1 0 1 0.53125 1 0 1 0 1 1 1 0 0.52500 1 0 1 0 1 1 1 1 0.51875 1 0 1 1 0 0 0 0 0.51250 1 0 1 1 0 0 0 1 0.50625 vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 voltage 1 0 1 1 0 0 1 0 0.50000 1 1 1 1 1 1 1 0 off 1 1 1 1 1 1 1 1 off
RT8862 6 ds8862-01 april 2011 www.richtek.com table 2. output voltage program (vrd10.x + vid6) to be continued pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 0 1 0 1 0 1 1 1.60000v 0 1 0 1 0 1 0 1.59375v 0 1 0 1 1 0 1 1.58750v 0 1 0 1 1 0 0 1.58125v 0 1 0 1 1 1 1 1.57500v 0 1 0 1 1 1 0 1.56875v 0 1 1 0 0 0 1 1.56250v 0 1 1 0 0 0 0 1.55625v 0 1 1 0 0 1 1 1.55000v 0 1 1 0 0 1 0 1.54375v 0 1 1 0 1 0 1 1.53750v 0 1 1 0 1 0 0 1.53125v 0 1 1 0 1 1 1 1.52500v 0 1 1 0 1 1 0 1.51875v 0 1 1 1 0 0 1 1.51250v 0 1 1 1 0 0 0 1.50625v 0 1 1 1 0 1 1 1.50000v 0 1 1 1 0 1 0 1.49375v 0 1 1 1 1 0 1 1.48750v 0 1 1 1 1 0 0 1.48125v 0 1 1 1 1 1 1 1.47500v 0 1 1 1 1 1 0 1.46875v 1 0 0 0 0 0 1 1.46250v 1 0 0 0 0 0 0 1.45625v 1 0 0 0 0 1 1 1.45000v 1 0 0 0 0 1 0 1.44375v 1 0 0 0 1 0 1 1.43750v 1 0 0 0 1 0 0 1.43125v 1 0 0 0 1 1 1 1.42500v 1 0 0 0 1 1 0 1.41875v 1 0 0 1 0 0 1 1.41250v 1 0 0 1 0 0 0 1.40625v 1 0 0 1 0 1 1 1.40000v 1 0 0 1 0 1 0 1.39375v 1 0 0 1 1 0 1 1.38750v 1 0 0 1 1 0 0 1.38125v 1 0 0 1 1 1 1 1.37500v 1 0 0 1 1 1 0 1.36875v 1 0 1 0 0 0 1 1.36250v
RT8862 7 ds8862-01 april 2011 www.richtek.com pin n ame vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 1 0 1 0 0 0 0 1.35625v 1 0 1 0 0 1 1 1.35000v 1 0 1 0 0 1 0 1.34375v 1 0 1 0 1 0 1 1.33750v 1 0 1 0 1 0 0 1.33125v 1 0 1 0 1 1 1 1.32500v 1 0 1 0 1 1 0 1.31875v 1 0 1 1 0 0 1 1.31250v 1 0 1 1 0 0 0 1.30625v 1 0 1 1 0 1 1 1.30000v 1 0 1 1 0 1 0 1.29375v 1 0 1 1 1 0 1 1.28750v 1 0 1 1 1 0 0 1.28125v 1 0 1 1 1 1 1 1.27500v 1 0 1 1 1 1 0 1.26875v 1 1 0 0 0 0 1 1.26250v 1 1 0 0 0 0 0 1.25625v 1 1 0 0 0 1 1 1.25000v 1 1 0 0 0 1 0 1.24375v 1 1 0 0 1 0 1 1.23750v 1 1 0 0 1 0 0 1.23125v 1 1 0 0 1 1 1 1.22500v 1 1 0 0 1 1 0 1.21875v 1 1 0 1 0 0 1 1.21250v 1 1 0 1 0 0 0 1.20625v 1 1 0 1 0 1 1 1.20000v 1 1 0 1 0 1 0 1.19375v 1 1 0 1 1 0 1 1.18750v 1 1 0 1 1 0 0 1.18125v 1 1 0 1 1 1 1 1.17500v 1 1 0 1 1 1 0 1.16875v 1 1 1 0 0 0 1 1.16250v 1 1 1 0 0 0 0 1,15625v 1 1 1 0 0 1 1 1.15000v 1 1 1 0 0 1 0 1.14375v 1 1 1 0 1 0 1 1.13750v 1 1 1 0 1 0 0 1.13125v 1 1 1 0 1 1 1 1.12500v 1 1 1 0 1 1 0 1.11875v to be continued
RT8862 8 ds8862-01 april 2011 www.richtek.com pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage d ac out 1 1 1 1 0 0 1 1.11250v 1 1 1 1 0 0 0 1.10625v 1 1 1 1 0 1 1 1.10000v 1 1 1 1 0 1 0 1.09375v 1 1 1 1 1 0 1 off 1 1 1 1 1 0 0 off 1 1 1 1 1 1 1 off 1 1 1 1 1 1 0 off 0 0 0 0 0 0 1 1.08750v 0 0 0 0 0 0 0 1.08125v 0 0 0 0 0 1 1 1.07500v 0 0 0 0 0 1 0 1.06875v 0 0 0 0 1 0 1 1.06250v 0 0 0 0 1 0 0 1.05625v 0 0 0 0 1 1 1 1.05000v 0 0 0 0 1 1 0 1.04375v 0 0 0 1 0 0 1 1.03750v 0 0 0 1 0 0 0 1.03125v 0 0 0 1 0 1 1 1.02500v 0 0 0 1 0 1 0 1.01875v 0 0 0 1 1 0 1 1.01250v 0 0 0 1 1 0 0 1.00625v 0 0 0 1 1 1 1 1.00000v 0 0 0 1 1 1 0 0.99375v 0 0 1 0 0 0 1 0.98750v 0 0 1 0 0 0 0 0.98125v 0 0 1 0 0 1 1 0.97500v 0 0 1 0 0 1 0 0.96875v 0 0 1 0 1 0 1 0.96250v 0 0 1 0 1 0 0 0.95625v 0 0 1 0 1 1 1 0.95000v 0 0 1 0 1 1 0 0.94375v 0 0 1 1 0 0 1 0.93750v 0 0 1 1 0 0 0 0.93125v 0 0 1 1 0 1 1 0.92500v 0 0 1 1 0 1 0 0.91875v 0 0 1 1 1 0 1 0.91250v 0 0 1 1 1 0 0 0.90625v 0 0 1 1 1 1 1 0.90000v to be continued
RT8862 9 ds8862-01 april 2011 www.richtek.com pin name vid4 vid3 vid2 vid1 vid0 vid5 vid6 nominal output voltage dacout 0 0 1 1 1 1 0 0.89375v 0 1 0 0 0 0 1 0.88750v 0 1 0 0 0 0 0 0.88125v 0 1 0 0 0 1 1 0.87500v 0 1 0 0 0 1 0 0.86875v 0 1 0 0 1 0 1 0.86250v 0 1 0 0 1 0 0 0.85625v 0 1 0 0 1 1 1 0.85000v 0 1 0 0 1 1 0 0.84375v 0 1 0 1 0 0 1 0.83750v 0 1 0 1 0 0 0 0.83125v
RT8862 10 ds8862-01 april 2011 www.richtek.com table 3. output voltage program (k8) vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.200 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 shutdown note: (1) 0 : connected to gnd (2) 1 : open
RT8862 11 ds8862-01 april 2011 www.richtek.com table 4. output voltage program (k8_m2) to be continued pin name vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 0 0 0 0 0 0 1.5500 0 0 0 0 0 1 1.5250 0 0 0 0 1 0 1.5000 0 0 0 0 1 1 1.4750 0 0 0 1 0 0 1.4500 0 0 0 1 0 1 1.4250 0 0 0 1 1 0 1.4000 0 0 0 1 1 1 1.3750 0 0 1 0 0 0 1.3500 0 0 1 0 0 1 1.3250 0 0 1 0 1 0 1.3000 0 0 1 0 1 1 1.2750 0 0 1 1 0 0 1.2500 0 0 1 1 0 1 1.2250 0 0 1 1 1 0 1.2000 0 0 1 1 1 1 1.1750 0 1 0 0 0 0 1.1500 0 1 0 0 0 1 1.1250 0 1 0 0 1 0 1.1000 0 1 0 0 1 1 1.0750 0 1 0 1 0 0 1.0500 0 1 0 1 0 1 1.0250 0 1 0 1 1 0 1.0000 0 1 0 1 1 1 0.9750 0 1 1 0 0 0 0.9500 0 1 1 0 0 1 0.9250 0 1 1 0 1 0 0.9000 0 1 1 0 1 1 0.8750 0 1 1 1 0 0 0.8500 0 1 1 1 0 1 0.8250 0 1 1 1 1 0 0.8000 0 1 1 1 1 1 0.7750 1 0 0 0 0 0 0.7625 1 0 0 0 0 1 0.7500
RT8862 12 ds8862-01 april 2011 www.richtek.com note: (1) 0 : connected to gnd (2) 1 : open (3) the voltage above are load independent for desktop and server platforms. for mobile platforms the voltage above correspond to zero load current. pin name vid5 vid4 vid3 vid2 vid1 vid0 nominal output voltage dacout 1 0 0 0 1 0 0.7375 1 0 0 0 1 1 0.7250 1 0 0 1 0 0 0.7125 1 0 0 1 0 1 0.7000 1 0 0 1 1 0 0.6875 1 0 0 1 1 1 0.6750 1 0 1 0 0 0 0.6625 1 0 1 0 0 1 0.6500 1 0 1 0 1 0 0.6375 1 0 1 0 1 1 0.6250 1 0 1 1 0 0 0.6125 1 0 1 1 0 1 0.6000 1 0 1 1 1 0 0.5875 1 0 1 1 1 1 0.5750 1 1 0 0 0 0 0.5625 1 1 0 0 0 1 0.5500 1 1 0 0 1 0 0.5375 1 1 0 0 1 1 0.5250 1 1 0 1 0 0 0.5125 1 1 0 1 0 1 0.5000 1 1 0 1 1 0 0.4875 1 1 0 1 1 1 0.4750 1 1 1 0 0 0 0.4625 1 1 1 0 0 1 0.4500 1 1 1 0 1 0 0.4375 1 1 1 0 1 1 0.4250 1 1 1 1 0 0 0.4125 1 1 1 1 0 1 0.4000 1 1 1 1 1 0 0.3875 1 1 1 1 1 1 0.3750
RT8862 13 ds8862-01 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 fbrtn negative remote sense pin of output voltage. 2 qr1 quick response setting pins for load transition. 3 qr2 quick response setting pins for load transition. 4 ss/en connect this pin to gnd by a capacitor to adjust soft start time. pull this pin to gnd to disable controller. 5 comp output of the error-amplifier and input of the pwm comparator. 6 fb inverting input of the error-amplifier. 7 ofs connect this pin to gnd or 5v by a resistor to set no-load offset voltage. 8 rt connect this pin to gnd by a resistor to adjust frequency. 9 adj connect this pin to gnd by a resistor to set load line. 10 imax negative input of ocp comparator. (positive input of ocp comparator is adj). 11 imaxpsi ocp setting in power saving mode. 12 imonfb current monitor gain/offset adjustment. 13 imon current monitor output. 14, 17, 18, 21 isp4, isp3, isp2, isp1 positive current sense pin of phase 1, 2, 3 and 4. 15, 16, 19, 20 isn4, isn3, isn2, isn1 negative current sense pin of phase 1, 2, 3 and 4. 22 vrhot temperature monitor output. 23 tsen temperature sense input. 24 vcc5 5v ldo output for system power supply. 25, 26 pwm4, pwm3 pwm output for phase 4 and phase 3. 27, 35 boot2, boot1 bootstrap supply for phase 2 and phase 1. 28, 34 ugate2, ugate1 upper gate driver for phase 2 and phase 1. 29, 33 phase2, phase1 switching node of phase 2 and phase 1. 30, 32 lgate2, lgate1 lower gate driver for phase 2 and phase 1. 31 vcc12 ic power supply. connect to 12v. 36 pwrgd power good indicator. 37 en/vtt vtt voltage detector input. 38 to 45 vid7 to vid0 voltage identification input for dac. 47 psi power status indicator ii. 48 ps dynamic phase control threshold input. 46 vidsel vid dac selection pin. 49 ( exposed pad) gnd the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. vidsel vid [7] ta bl e vtt x vr11 gnd x vr1 0.x vcc5 vtt k8 vcc5 gnd k8_m2 vid table selection
RT8862 14 ds8862-01 april 2011 www.richtek.com function block diagram vcc12 vcc5 boot1 ugate1 phase1 lgate1 boot2 ugate2 phase2 lgate2 pwm3 pwm4 isp1 isn1 isp2 isn2 isp3 isn3 isp4 isn4 adj fbrtn vid7 to vid0 i_sen1 i_sen2 i_sen3 i_sen4 imax/ imaxpsi oc por por vidoff ss/en fb 150mv ov comp oc ov rt 850mv en/vtt ofs vrhot tsen power-on reset 5v regulator mosfet driver mosfet driver ch1 current sense ch2 current sense ch3 current sense ch4 current sense avg vid table generator temperature monitor transient response enhancement offset modulator waveform generator + - + - + - + - + - + - + + - + + - ea + - + - + - + - + - load current monitor imon imonfb vidsel qr1/qr2 gnd dynamic phase control psi oe4 oe3 oe2 oe1 ps imon soft start and fault logic iofsn iofsp
RT8862 15 ds8862-01 april 2011 www.richtek.com electrical characteristics parameter symbol test conditions min typ max unit vcc12 supply input vcc12 supply voltage vcc12 10.8 12 13.2 v vcc12 supply current i cc -- 6 -- ma vcc5 power vcc5 supply voltage vcc5 i lo ad = 10ma (note 6) 4.75 5.0 5.25 v vcc5 output sourcing i vcc5 10 -- -- ma power on reset vcc12 rising threshold v vcc12th vcc12 rising 9.2 9.6 10 v vcc12 hysteresis v vcc12hy vcc12 falling -- 0.9 -- v vcc5 rising threshold v vcc5th 4.4 4.6 4.8 v vcc5 hysteresis v vcc5hy -- 0.4 -- v to be continued recommended operating conditions (note 4) z supply voltage, vcc12 ---------------------------------------------------------------------------------------- 12v 10% z junction temperature range ---------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range ---------------------------------------------------------------------------------- 0 c to 70 c absolute maximum ratings (note 1) z supply input v oltage ------------------------------------------------------------------------------- ? 0.3v to 15v z bootx to phasex -------------------------------------------------------------------------------- ? 0.3v to 15v z phasex to gnd dc ------------------------------------------------------------------------------------------------------ ? 2v to 15v < 20ns ------------------------------------------------------------------------------------------------- ? 5v to 30v z ugatex to gnd ------------------------------------------------------------------------------------ (v phase ? 0.3v) to (v boot + 0.3v) < 20ns ------------------------------------------------------------------------------------------------- (v phase ? 5v) to (v boot + 5v) z lgatex to gnd ------------------------------------------------------------------------------------- (gnd ? 0.3v) to (v cc + 0.3v) < 20ns ------------------------------------------------------------------------------------------------- (gnd ? 5v) to (v cc + 5v) z others pins ------------------------------------------------------------------------------------------ ? 0.3v to 6.5v z input/output v oltage ------------------------------------------------------------------------------- ? 0.3v to (vcc5 + 0.3v) z power dissipation, p d @ t a = 25 c wqfn ? 48l 7x7 ------------------------------------------------------------------------------------- 2.941w z package thermal resistance (note 2) wqfn ? 48l 7x7, ja ------------------------------------------------------------------------------- 34 c/w wqfn ? 48l 7x7, jc ------------------------------------------------------------------------------- 7 c/w z junction temperature ------------------------------------------------------------------------------ 150 c z lead temperature (soldering, 10 sec.) -------------------------------------------------------- 260 c z esd susceptibility (note 3) hbm (human body mode) ------------------------------------------------------------------------ 2kv mm (machine mode) ------------------------------------------------------------------------------- 200v (vcc12 = 12v, v gnd = 0v, t a = 25 c, unless otherwise specified)
RT8862 16 ds8862-01 april 2011 www.richtek.com parameter symbol test conditions min typ max unit en/vtt en/ vtt rising th re sho ld v envtt en/vtt rising 0.8 0.85 0.9 v enable hysteresis v envtthy en/vtt falling -- 100 -- mv reference voltage accuracy 1v to 1.6v ? 0.5 -- 0. 5 % 0.8v t o 1v ? 5 -- 5 mv dac accuracy 0.5v t o 0.8v ? 8 -- 8 mv error amplifie r dc gain a dc no load -- 80 -- db gain-bandwidth gbw c load = 10pf -- 10 -- mhz slew rate sr c load = 10pf 10 -- -- v/ s output voltage range v comp 0. 5 3. 6 v max current i ea_s lew slew 300 -- -- a power se quence pwrgd low voltage v pgood i pwrgd = 4ma -- -- 0. 4 v soft-start delay t d1 -- 2 -- ms v boot duration t d3 -- 0.8 -- ms pwrgd delay t d5 measured the time form v boot change to pwrgd = 1 -- 1.6 -- ms current sense amplifier max current i gmmax v csp = 1.3v sink current from csn 100 -- -- a input offset voltage v oscs ? 2 0 2 mv running frequency f osc r rt = 40 k 270 300 330 kh z rt pin voltage v rt r rt = 40 k 0.76 0.8 0.84 v ramp slope v ramp r rt = 40 k -- 22 -- %/v soft start soft start current i ss1 slew 12 16 20 a vid change c urrent i ss2 slew 120 160 200 a gate driver ugate drive source r ugatesr boot ? phase = 8v 250ma source current -- 1 -- ugate drive sink r ugatesk boot ? phase = 8v 250ma sink current -- 1 -- lgate drive source r lgatesr v lgate = 8 v -- 1 -- lgate drive sink r lgatesk 250ma sink current -- 0.8 -- protection over-voltage threshold v ovp sweep fb voltage, v fb ? v eap 125 150 175 mv over-current threshold v ocp sweep imax voltage, v im ax ? v adj ? 10 0 10 mv to be continued
RT8862 17 ds8862-01 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective four layers thermal conductivity test board of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. the maximum output voltage of power monitor will be restricted by en/vtt pin input voltage. note 6. test condition : RT8862 normal operating, an extra static dc current load 10ma applying at vcc5 pin. parameter symbol test conditions min typ max unit dynamic characteristic ugate rise time t rugate -- 15 -- ns ugate fall time t fugate -- 10 -- ns lgate rise time t rlgate -- 15 -- ns lgate fall time t flgate ciss = 3000p -- 10 -- ns current sourcing from ps pin to set v ps2 i ps when v ps2 is needed by control circuit 86.4 96 105.6 a input threshold vid7 to vid0, vidsel rising threshold v id7 to 0 , v idsel vid7 to vid0 rising, vidsel rising -- 1/2v tt + 12.5mv -- v vid7 to vid0 hysteresis v id7 to 0_hy vid7 to vid0 falling -- 25 -- mv psi rising threshold v psi psi rising -- 1/2v tt + 12.5mv -- v
RT8862 18 ds8862-01 april 2011 www.richtek.com typical operating characteristics dynamic vid up time (100 s/div) vid from 0.8v up to 1.4v, i load = 85a vid1 (1v/div) v out (500mv/div) dynamic vid down time (100 s/div) vid from 1.4v down to 0.8v, i load = 85a vid1 (1v/div) v out (500mv/div) load transient response time (100 s/div) vid = 1.4v, f load = 200hz, i load = 100a to 35a v out (20mv/div) -> 1.3v i load 35a 100a time (400 s/div) power off from en/vtt vid = 1.4v, i load = 5a en/vtt (1v/div) v out (1v/div) pwrgd (1v/div) ugate (20v/div) vid = 1.4v, i load = 5a time (1ms/div) power on from en/vtt en/vtt (1v/div) v out (1v/div) pwrgd (1v/div) ugate (20v/div) load transient response time (100 s/div) vid = 1.4v, f load = 200hz, i load = 35a to 100a v out (20mv/div) -> 1.3v i load 35a 100a
RT8862 19 ds8862-01 april 2011 www.richtek.com current monitor output voltage vs. load current 0.0 0.2 0.4 0.6 0.8 1.0 0 22446688110 load current (a) current monitor output voltage (v ) time (40 s/div) over voltage protection pwrgd (1v/div) fb (1v/div) ugate (20v/div) lgate (10v/div) time (200 s/div) over current protection pwrgd (1v/div) v out (1v/div) ugate (20v/div) i load (100a/div) thermal monitoring time (500 s/div) tsen from 0v sweep to 5v, i load = 0a vrhot (1v/div) tsen (2v/div)
RT8862 20 ds8862-01 april 2011 www.richtek.com figure 4. circuit for soft start and dynamic vid the v out start-up time is set by a capacitor from the ss pin to gnd. in power_on_reset state (por = l), the ss pin is held at gnd. after power_on_reset stae (por = h) and an extra delay of 1600 s, v ss and v ssq begin to rise till v ssq = v boot . when v ssq = v boot , the RT8862 stays in this state for 800 s, waiting for valid vid code sent by cpu. after receiving valid vid code, v out continues ramping up or down to the voltage specified by vid code. before pwrgd = h, output current of opss (i ss ) is limited to a (i ss1 ). when pwrgd = h, i ss is limited to 80 a (i ss2 ). the soft start waveform is sh own in figure 5. + - opss v dac ss + - adj c ss r adj ntc eap (erroramp positive input) output current of opss (i ss ) is limited and variant ssq soft start application information the RT8862 is a 4/3/2/1-phase synchronous buck dc/dc converter with 2 embedded mosfet drivers. the internal vid dac is designed to interface with the intel vr11.x/ 10.x and amd k8/k8_m2 compatible cpus. power ready detection during start-up, the RT8862 will detect vcc12, vcc5 and v tt . when vcc12 > 9.6v, vcc5 > 4.6v and v tt > 0.85v, por will go high. por (power on reset) is the internal signal to indicate all powers are ready to let the RT8862 and the companioned mosfet drivers work properly. when por = l, the RT8862 will try to turn off both high side and low side mosfets. phase detection the number of operational phases is determined by the internal circuitry that monitors the isnn voltages during start up. normally, the RT8862 operates as a 4-phase pwm controller. pull isn4 and isp4 to vcc5 programs 3-phase operation. pull isn3 and isp3 to vcc5 programs 2-phase operation. the RT8862 detects the voltage of isn4 and isn3 por rising edge. at the rising edge, the RT8862 detects whether the voltage of isn4 and isn3 are higher than ? vcc5 ? 1v ? respectively to decide how many phases should be active. phase detection is only active during start up. when por = h, the number of operational phases is determined and latched. the unused pwm pins can be connected either to 5v, gnd or left floating. phase switching frequency the phase switching frequency of the RT8862 is set by an external resistor connected from the rt pin to gnd. the frequency follows the graph in figure 2. figure 1. circuit for power ready detection figure 2. r rt vs phase switching frequency por vcc12 v tt + - cmp + - cmp + - cmp por : power on reset 9.6v 4.6v 0.85v vcc5 frequency vs. r rt 0 200 400 600 800 1000 1200 0 40 80 120 160 200 240 280 r rt (k ohm) frequency (khz) (k )
RT8862 21 ds8862-01 april 2011 www.richtek.com figure 5. soft start waveforms v out will trace v eap which is equal to ? v ssq ? v adj ? . v adj is a small voltage signal which is proportional to i out . this voltage is used to generate loadline and will be described later. t1 is the delay time from power_on_reset state to the beginning of v out rising. t1 = 1600 s + 0.6v x c ss / i ss1 (1) t2 is the soft start time from v out = 0 to v out = v boot . t2 = v boot x c ss / i ss1 (2) t3 is the dwelling time for v out = v boot . t3 = 800us. t4 is the soft start time from v out = v boot to v out = v dac . t4 ~= |v dac - v boot | x c ss /i ss1 (3) t5 is the power good delay time, t5 ~= 1600 s. dynamic vid the RT8862 can accept vid input changing while the controller is running. this allows the output voltage (v out ) to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (otf). a vid otf can occur under either light or heavy load conditions. the cpu changes the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. theoretically, v out should follow v dac which is a staircase waveform. in RT8862, as mentioned in soft start session, v dac slew rate is limited by i ss2 /c ss when pwrgd = h. this slew rate limiter works as a low pass filter of v dac and makes the bandwidth of v dac waveform finite. by smoothening v dac staircase waveform, v out will no longer overshoot or undershoot. on the other hand, c ss will increase the settling time of v out during vid otf. in most cases, 1nf to 30nf ceramic capacitor is suitable for c ss . output voltage differential sensing the RT8862 uses differential sensing by a high gain low offset error amplifier. the cpu voltage is sensed between the fb and fbrtn pins. a resistor (r fb ) connects fb pin and the positive remote sense pin of the cpu (v ccp ). fbrtn pin connects to the negative remote sense pin of cpu (v ccn ) directly. the error amplifier compares eap (= v dac ? v adj ) with the v fb to regulate the output voltage. no load offset in figure 6, i ofsn or i ofsp are used to generate no-load offset. either i ofsn or i ofsp is active during normal operation. it should be noted that users can only enable one polarity of no-load offset. do not connect ofs pin to gnd and to v cc5 at the same time. connect a resistor from ofs pin to gnd to activate i ofsn . i ofsn flows through r adj from adj pin to gnd. in this case, negative no-load offset voltage (v ofsn ) is generated. v ofsn = i ofsn x r adj = 0.8 x r adj /r ofs (4) vcc12 9.6v v dac ss ssq pwrgd t1 t2 t3 v tt 0.85v v boot t4 t5 ss ssq vcc5 4.6v connect a resistor from ofs pin to v cc 5 to activate i ofsp . i ofsp flows through r fb from the v ccp to fb pin. in this case, positive no-load offset voltage (v ofsp ) is generated. when ofs pin is connected to vcc5 through a resistor, the positive no-load offset can be calculated as : the RT8862 provides wide range no-load positive offset for over-clocking applications. the i ofsp capability can supply from 30 a to 640 a, which means in equation (5), r ofs can range from 240k to 10k . other resistances of r ofs exceeding this range can also provide no-load positive offset but cannot be guaranteed by equation (5). (5) fb ofsp ofsp fb ofs r vir6.4 r ==
RT8862 22 ds8862-01 april 2011 www.richtek.com figure 7 figure 6. circuit for v out differential sensing and no load offset + - ea + - v dac + - i ofsn eap comp fb fbrtn adj c1 c2 r1 c fb r fb v ccp (positive remote sense pin of cpu) v ccn (negative remote sense pin of cpu) r adj i ofsp l/dcr = r s x c s (6) then the output current of csa will follow the equation below : i x = [i l x dcr ? v ofs-csa + 235n x (r csp ? r csn )] /r csn (7) 235na is typical value of csa input offset current. v ofs-csa is the input offset voltage of csa. v ofs-csa of RT8862 is smaller than +/- 1mv. usually, ? v ofs-csa + 235n x (r csp ? r csn ) ? is negligible except at very light load and the equation can be simplified as the equation below : i x = i l x dcr/r csn (8) loadline output c urrent of csa is summed and averaged in the RT8862. then 0.5 (i x [n]) is sent to adj pin. because i x [n] is a ptc (positive temperature coefficient) current, an ntc (negative temperature coefficient) resistor is needed to connect adj pin to gnd. if the ntc resistor is properly selected to compensate the temperature coefficient of i x [n], the voltage on adj pin will be proportional to i out without temperature effect. in the RT8862, the positive input of error amplifier is ? v dac ? v adj ? . v out will follow ? v dac ? v adj ? , too. thus, the output voltage decreasing linearly with i out is obtained. the loadline is defined as ll(loadline) = v out / i out = v adj / i out = 0.5 x dcr x r adj /r csn (9) briefly, the resistance of r adj sets the resistance of loadline. the temperature coefficient of r adj compensates the temperature effect of loadline. current balance in figure 8, i x [n] is the current signal which is proportional to current fl owing through phase n. in figure 9, the current error signals i err n (= i x [n] ? avg(i x [n])) are used to raise or lower the internal sawtooth waveforms (ramp[1] to ramp[n]) which are compared with error amplifier output (comp) to generate pwm signal. the raised sawtooth waveform will decrease the pwm duty of the corresponding phase while the lowered will increase. eventually, current flowing through each phase will be balanced. load transient quick response the RT8862 utilizes a new quick response feature to supply heavy load current demand during instantaneous load application transient. the RT8862 detects load transient and reacts via vout pin. when vout drops during load application transient,the quick response comparator will send asserted signals to turn on high side mosfets and turn off low side mosfets. the qr signal will turn on all phase's high side mosfets while turning off low side mosfets also. therefore, the influence of total quick response function of RT8862 is adjustable, and the magnitude of quick response is flexible via fine-tuning the resistor connected to qr1 or qr2 pin. i out v out qr output current sensing the RT8862 provides low input offset current-sense amplifier (csa) to monitor the output current of every phase. output current of csa (i x [n]) is used for phase current balance and active voltage position. in this inductor current sensing topology, r s and c s must be set according to the equation below :
RT8862 23 ds8862-01 april 2011 www.richtek.com + - + - + - + - comp i err [1] x r cb i err [n] x r cb interleaved ramp[1] ramp[n] cmp cmp buf buf pwm[1] pwm[n] figure 9. circuit for phase current balance adjusting phase current if phase current is not balanced due to asymmetric pcb layout of power stage, external resistors can be adjusted to correct current imbalance. figure 10 shows two types of current imbalance, constant ratio type and constant difference type. if the initial current distribution is constant ratio type, according to equation (8), reduce r csn [1] can reduce i l [1] and improve current balance. if the initial current distribution is constant difference type, according to equation (7), increase r csp [1] can reduce i l [1] and improve current balance. figure 8. circuit for phase current sensing constant ratio i out , total i1 i2 constant difference i out , total i1 i2 figure 10. phase current vs. total current over current protection (ocp) RT8862 provides single phase ocp and multi-phase ocp according to the operation condition. in figure 11, single phase ocp (imaxpsi) and multi-phase ocp (imax) thresholds can be set by external resistors : imax cc5 imaxpsi cc5 r2 + r3 vv r1 + r2 + r3 r3 vv r1 + r2 + r3 = = (10) (11) once v adj is larger than the negative input of cp comparator, ocp will be triggered and latched, and RT8862 will turn off both high side and low side mosfets of all phases. a 20us delay after ocp detection is used to prevent false trigger. over voltage protectiom (ovp) the over voltage protection monitors the output voltage via the fb pin. once v fb exceeds ? v eap + 150mv ? , ovp is triggered and latched. RT8862 will try to turn on low side mosfet and turn off high side mosfet to protect cpu. a 20us delay is used in ovp detection circuit to prevent false trigger. + - 235na 235na v ofs_csa + - isn isp r isp r isn r s dcr c s l i x csa: current sense amplifier
RT8862 24 ds8862-01 april 2011 www.richtek.com output current monitoring (imon) the RT8862 senses load current and output a voltage signal to indicate the instantaneous load current status. since the sensed total current is injected into the resistors connected to adj pin, adj voltage than is used for imon function as shown in figure 12. through the resistor network r1, r2 and r3, imon voltage will be proportional to adj pin voltage according to the equation : imon adj tt r3 r3 vvv r1 // r2 // r3 r1 =? (12) figure 12. output current monitoring thermal monitoring (vrhot) the RT8862 provides thermal monitoring function via sensing tsen pin voltage. through the voltage divider r1 and r ntc , the voltage of tsen is typically set to be higher than 0.33 x v cc5 when ambient temperature is lower than vrhot assertion target. when ambient temperature rises, tsen voltage will fall, and vrhot signal will be set to high if tsen voltage drops below 0.28 x v cc5 . accordingly, vrhot will be reset to low once tsen voltage rises above 0.33 x v cc5 . correctly choose the resistance of r1 and r ntc can assert and de-assert vrhot accurately at target ambient temperature. figure 13. thermal monitoring figure 11. over current protection + - adj imax v cc5 r1 r2 ocp imaxpsi r3 + - v cc5 /v tt r3 r2 r1 adj imonfb v tt imon power state indicator (psi) the RT8862 supports psi# function for vr11.1 cpus and platform users. the RT8862 will monitor psi pin input voltage to change the operating state. when psi is high (higher than 1/2 v tt + 12.5mv), the RT8862 operates as a full-phase interleaving pwm controller and all phases are active. when input voltage is low (lower than v tt + 12.5mv), the RT8862 will change to single phase operation mode and only phase 1 is active. since phase 2 includes embedded driver, the RT8862 will automatically disable phase 2 by forcing ugate2 and lgate2 into high impedance state when input voltage is low. the RT8862 will also disable phase 3 and phase 4 by sending continuous tri-state signals (~2.5v) from pwm3 and pwm4 to external drivers when input voltage is low. therefore, 2 external drivers which support tri-state shutdown should be used if psi function is considered, and the rt9619 is recommended to be the external drivers for vr11.1 compatibility. during psi asserted period, e.g., input voltage is low, if the RT8862 receives dynamic vid change command, the RT8862 will enter interleaving mode operation and all phases will be activated. psi command will be ignored during dynamic vid operation, and psi will be blanked for about 100us after dynamic vid change is completed. dynamic phase control RT8862 has the ability of automatically control phase numbers according to the total load current. this feature optimizes system efficiency over a wide load range. connect a resistive voltage divider to ps pin to define the two thresholds, v ps1 and v ps2 , for the dynamic phase control. because the imon pin voltage (v imon ) represents the total current, the controller compares ps pin voltage (v ps1 and v ps2 ) with v imon to decide the number of operating phase. see table 1 for the dynamic phase control mechanism. + - 0.28 x v cc5 + - 0.33 x v cc5 r q s vrhot tsen v cc5 r1 r ntc
RT8862 25 ds8862-01 april 2011 www.richtek.com operating phases v ps1 v ps2 max. phase=4 max. phase=3 max. phase=2 < v imon < v imon 4-phase operation 3-phase operation 2-phase operation < v imon > v imon 3-phase operation 2-phase operation 2-phase operation > v imon > v imon 2-phase operation 1-phase operation 1-phase operation table 1 if max. phase number = 3, it means phase 4 is disabled by pulling isn4 to 5v before power up. if max. phase number = 2, it means phase 4 and phase 3 are disabled by pulling isn4 and isn3 to 5v before power up. the imon pin voltage of RT8862 is clamped below vcc5. users can get more design flexibility to implement auto phase control feature by higher imon voltage. note that the linearity of imon can be guaranteed when v imon < 2.5v. a 1 f bypass capacitor connected to a clean ground is necessary at imon pin. further more, the RT8862 utilizes true interleaving during auto phase shedding process. i.e. 4-phase : 90 , 3-phase : 120 , and 2-phase : 180 . by doing so, ripple uniformity is guaranteed in steady state. dynamic phase control principles the RT8862 change to higher number of phase operation when v imon is higher than v ps1 or v ps2 . no hysteresis and extra delay exists during an up phase decision. however, hysteresis (v hys ) and delay exist during a down phase decision. RT8862 triggers a timer when v imon is lower than (v ps1 - v hys ) or (v ps2 -v hys ), and persisted a certain amount of time, the controller goes to lower phase number operation. the timer is designed as long as 2047 switching cycles. therefore, if the switching frequency is chosen at 300khz, the timer is about 2047x(1/300khz) = 6.82ms. the v hys value is always proportional to v ps . i.e. v hys =k x v ps . where when 2 phases operation down to 1 phase, and for all other cases. when quick response is triggered, the RT8862 goes back to full-phase operation immediately. r2 r1 vcc 5v i ps ps pin r t 8 8 6 2 ps1 ps2 ps ps1 ps ps ps1 ps ps2 ps1 r1 5 r1 v = 5 x = , = r1+r2 1+ r2 r1 v = 5 x + i x (r1//r2) r1+r2 r1r2 = v + i x r1+r2 ir1 = v + +1 ir1 v - v = +1 figure 14. v ps1 and v ps2 setting and equations for example, if v ps2 is designed as 1v and the hysteresis is 0.25v, the down phase operation can only take place when v imon is continuously lower than 0.75v for 6.82ms (if switching frequency is 300khz). note that ,if RT8862 received a qr command it will change to maximum phase interleaving operation. howerve,if psi signal assert, the RT8862 will down to single phase operation directly, although v imon is higher than v ps . setting dynamic phase control threshold (v ps1 , v ps2 ) v ps1 and v ps2 can be set by the ps pin resistors. in figure 14, v ps1 is defined only by the resistive voltage divider r1 and r2 . but v ps2 is defined by i ps , r1 and r2 altogether . the calculation is listed in figure 14. to decide the value of r1 and r2, , one must choose the target threshold current for auto down phase, calculate v ps1 and v ps2 , and then use the equations in figure 14 to calculate r1 and r2. . the calculation is very easy. an example is provided as follows : a bypass capacitor is recommended at ps pin. but the capacitor must be smaller than 200pf to keep the circuit in normal function. ps1 ps1 5 v = 0.01 x 32 = 0.32 (v) , v = = 0.068 1+ ? design example : 1. derive v imax vs. total current relationship : assume we have a platform with v imax = 1v represents maximum current = 100a, so 10mv represents 1a can be drived. 2. to set first threshold to 32a, 3. to set second threshold to 48a, ps2 ps2 ps1 ps v = 0.01 48 = 0.48 (v), v v = 0.16 (v) ir1 96 a r1 = = r1 = 1.78k + 1 + 1 ? ? 4. r2 = r1/ = 26.176k 6 k = 20 4 k = 20
RT8862 26 ds8862-01 april 2011 www.richtek.com 2 2 in d v g ss 1 l 1 r c lc = ++ ?? ?? ?? (13) and the modulator gain of the converter is : m p 1 f v = (14) where v out is the output voltage of the converter, r is the loading resistance, l and c are the output inductance and capacitance, and v p is the peak-to-peak voltage of ramp applied at modulator input. the overall loop gain after compensation can be described as : loop gain = t = g d x f m x a (15) where a denotes as compensation gain. to compensate a typical voltage mode buck converter, there are two ordinary compensation schemes, well known as type-ii compensator and type-iii compensator. the choice of using type-ii or type-iii compensator will be up to platform designers, and the main concern will be the position of the capacitor esr zero and mid-frequency to high- frequency gain boost. typically, the esr zero of output capacitor will tend to stabilize the effect of output lc double poles, hence the positon of the output capacitor esr zero in frequency domain may influence the design of voltage loop compensation. if f zero,esr is <1/2f co where f co denotes cross-over frequency, type-ii compensation will be sufficient for voltage stability. if f zero,esr is > 1/2f co (or higher gain and phase margin is required at mid- frequency to high-frequency), then type-iii compensation may be a better solution for voltage loop compensation. a typical type-ii compensation network is shown in figure 15. + - r2 c1 c2 r1 + - v ref ea r1 can be determined independently from dc considerations. normally choose r1 that the current passing by will be around 1ma. therefore, ref v r1 1ma = (16) then determine r2 by the boosted gain of loop gain at crossover : 2 zero, esr co p in(max) lc zero, esr f f v r2 r1 vff ?? = ?? ?? (17) where v in(max) is the max input voltage of power stage, v p is the peak-to-peak voltage of ramp applied at modulator input, f zero,esr is the frequency of output capacitor esr zero, and f lc is the frequency of output lc : zero, esr esr lc 1 f 2r c 1 f 2lc = = (18) (19) after determining the phase margin at crossover frequency, the position of zero and pole produced by type-ii compensation network, f z and f p, can then be determined. the bode plot of type-ii compensation is shown in figure15, where figure 16. bode plot of type-ii compensation gain (db) frequency (hz) f z f p loop compensation the RT8862 is a synchronous buck converter with two control loops : voltage loop and current balance loop. since the function of the current balance loop is to maintain the current balance between each active phase, its influence to converter stability will be negligible compared with the voltage feedback loop. therefore, to compensate the voltage loop will be the main task to maintain converter stability. the converter duty-to-output transfer function g d is : figure 15. type-ii compensation
RT8862 27 ds8862-01 april 2011 www.richtek.com z p 1 f 2r2c1 1 f 2 r2 (c1 // c2) = = (20) (21) f z can be determined by the following equation : -1 -1 -1 co z zco co zero, esr f f tan tan 90 ff f p.m. tan f ?? ?? ? ?? ?? ?? ?? ?? +? ?? ?? d (22) by properly choosing f z to fit equation (22), c1 can then be determined by : z 1 c1 2r2f = (23) and c2 can be determined by : 2 co z 1 c2 f 1 2r2 fc1 = ? (24) a typical type-iii compensation contains two zeros and two poles where the extra one zero and one pole compared with type-ii compensation are added for stabilizing the system when esr zero is relatively far from lc double poles in frequency domain. figure16. and figure.17 shows the typical circuit and bode plot of the type-iii compensation. figure 17. type-iii compensation + - r2 c1 c2 r1 + - v ref ea r3 c3 figure 18. bode plot of the type-iii compensation gain (db) frequency (hz) f z = f z1 = f z2 f p = f p1 = f p2 in typical application, the fz2 and fp2 are usually designed closed fz1 and fp1 respectively so, the following equation can be derived, after determining desired phase margin, according to the following equation : -1 -1 2 co z zco co p z f f p.m. tan tan 45 ff2 and f f = f ?? ?? ?+ ?? ?? ?? ?? d (25) (26) f z and f p can be determined by choosing proper f co to f z ratio to meet equation (25). again, r1 can be determined by the equation (16). r2 can be determined by the following equation : 2 co pz in(max) lc co f vf r2 r1 vff ?? = ?? ?? (27) other component values of the type-iii compensation can then be calculated as : z p z p 1 c1 2r2f 1 c2 1 2r2f c1 1 c3 2r1f 1 r3 2c3f = = ? = = (28) (29) (30) (31) thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = ( t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8862, the maximum junction temperature is 125 c. the junction to ambient thermal resistance ja is layout dependent. for wqfn-48l 7x7 packages, the thermal
RT8862 28 ds8862-01 april 2011 www.richtek.com layout considerations for best performance of the RT8862, the following guidelines must be strictly followed : ` input bulk capacitors and mlccs have to be put near high side mosfets. the connection plane of input capacitors and high side mosfets then can be kept as square as possible. ` the shape of phase planes (the connection plane between high side mosfets, low side mosfets and output inductors) have to be as square as possible. long traces, thin bars or separated islands must be avoided in phase planes. ` keep snubber circuits or damping elements near its objects. phase rc snubbers have to be close to low side mosfets, ugate damping resistors have to be resistance ja is 34 c/w on the standard jedec 51-7 four layers thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (34 c/w) = 2.941w for wqfn-48l 7x7 the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8862 package, the figure 19 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. figure 19. derating curves for RT8862 packages 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w) wqfn-48l 7x7 four layers pcb close to high side mosfets, and boot to phase damping resistors have to be close to high side mosfets and phase planes. also keep the traces of these snubbers circuits as short as possible. ` the area of v in plane (power stage 12v v in ) and v out plane (output bulk capacitors and inductors connection plane) have to be as wide as possible. long traces or thin bars must be avoided in these planes. the plane trace width must be wide enough to carry large input/ output current (40mil/a). ` the following traces have to be wide and short : ugate, lgate, boot, phase, and vcc12. make sure the width of these traces are wide enough to carry large driving current(at least 40mil). ` the voltage feedback loop contains two traces, vcc and vss, which are kelvin sensed from cpu socket or output capacitors. these two traces are suggested above 10mil width and put away from high (di/dt) switching elements such as high side mosfets, low side mosfets, phase plane etc. the circuit elements of voltage feedback loop, such as feedback loop short resistors and voltage loop compensation rcs, have to be kept near the RT8862 and also away from switching elements. ` the current sense mechanism of the RT8862 is fully differential kelvin sense. therefore, the current sense loops of the RT8862 contain two traces : the positive traces(isp1 to isp4) come from the positive node of output inductors(the node connecting phase plane) and the negative traces (isn1 to isn4) come from the negative node of output inductors(the node connecting output plane). do not connect the current sense traces from phase plane or output plane. only connect these traces from both sides of output inductors can achieve the goal of precise kelvin sense. the current sense feedback loops have to be routed away from switching elements, and the current sense rc elements have to be put near their respective isn or isp pins of the RT8862 and also away from noise switching elements. at lease 10 mil width is suggested for current sense feedback loops.
RT8862 29 ds8862-01 april 2011 www.richtek.com information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 d 6.950 7.050 0.274 0.278 d2 5.050 5.250 0.199 0.207 e 6.950 7.050 0.274 0.278 e2 5.050 5.250 0.199 0.207 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 48l qfn 7x7 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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